About

Rahul Kumar Tiwari is a highly experienced Principal Engineer at Western Digital with over 11 years of relevant experience. He is an expert in component debug activities, working on key issues during initial silicon bring up, issues limiting product performance and health. Rahul has extensive experience leading cross-functional teams to drive silicon debug activities across Intel SoCs product lines to improve early-stage silicon issues, yield improvement, and product test coverage enhancement. Prior to his current role, Rahul worked at Intel as a Technical Lead, mentoring a team of engineers responsible for handling SoC Scan Chain debug, MBIST, and EPBIST Test failure Debug (L2/L3 Cache). He was also involved closely with relevant teams for Pre Silicon activities, performing various pre Si simulations to get more debug coverage confidence before silicon arrival. Rahul has worked with high-end Silicon Debug/Probe equipment/FA tools LADA, LVX, IREM, FIB circuit edits. At Western Digital, Rahul has worked as a Senior Product Test Engineer, where he directly managed the Component Self-Test Project (FW based In house developed memory tester) at Factory execution level from scratch. He was involved in early engineering sample Qual., driven the Tester & Test program level improvements, test code optimization, test time reduction, Qual. & LVM. Rahul also developed a new method to detect the invalid Memory Test read failures caused by aged Tester sockets, released new test screens to detect these bad sockets & later Auto socket off based on-screen data. Rahul holds a Master of Technology (M.Tech.) degree in the Department of Electronics, Fiber Optics & Optical Communication System Engineering from the Indian Institute of Technology, Kharagpur. He has also completed his Senior Secondary Certificate from SSM Jabalpur and Secondary School Certificate from SSU Seoni. Rahul's TechStack includes test, Senior Software Engineer, and SDET. He is a highly skilled engineer with a proven track record of delivering results.